The present invention is directed memory devices, and, more particularly, to a system and method for allowing dynamic random access memory devices to be used as cache memory.
Memory devices are used in a wide variety of applications, including computer systems. Computer systems and other electronic devices containing a microprocessor or similar device typically include system memory, which is generally implemented using dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). The primary advantage of DRAM is that it uses relatively few components to store each bit of data, and is thus a relatively inexpensive means for providing system memory having a relatively high capacity. A disadvantage of DRAM, however, is DRAM memory cells must be periodically refreshed. While an array of memory cells is being refreshed, it cannot be accessed for a read or a write memory access. The need to refresh DRAM memory cells does not present a significant problem in most applications, but it can prevent the use of DRAM in applications where immediate access to memory cells is required or highly desirable. For example, if a row of memory cells is being refreshed when a command is received to read data from or write data to one or more memory cells in a row, the data cannot be read or written until the refresh has been completed because the refresh cannot be interrupted. The reason for this limitation will be apparent when one considers the events occurring during a refresh. Initially, the digit lines in the array containing the row being refreshed are equilibrated. The row line of the row being refreshed is then fired, thereby coupling memory cell capacitors in that row to respective digit lines. At that point, the data stored in that row would be lost if the refresh was terminated. The refresh process must therefore be allowed to continue before data are written to the row being refreshed. According, each digit line pair is coupled to a sense amplifier, which begins driving the digit lines toward two opposite power supply voltages corresponding to the data that was stored in the memory cell coupled to the digit line. When the digit lines have been driven to these voltages, the row is closed to isolate the memory cell capacitators from the digit lines, the digit lines are isolated from the sense amplifiers, and the digit lines are equilibrated (although not necessarily in that order). It is only after all of these steps have been completed that data can be written to one or more memory cells. As a result, there can be a substantial delay before data can be written to any row in the array being refreshed or read from other rows that are not being refreshed.
Also included in many computer systems and other electronic devices is a cache memory. The cache memory stores instructions and/or data (collectively referred to as xe2x80x9cdataxe2x80x9d) that are frequently accessed by the processor or similar device, and may be accessed substantially faster than instructions and data can be accessed in system memory. It is important for the processor or similar device to be able to access the cache memory as needed. If the cache memory cannot be accessed for a period, the operation of the processor or similar device must be halted during this period.
Cache memory is typically implemented using static random access memory (xe2x80x9cSRAMxe2x80x9d) because such memory need not be refreshed and is thus always accessible for a write or a read memory access. However, a significant disadvantage of SRAM is that each memory cell requires a relatively large number of components, thus making SRAM data storage relatively expensive. It would be desirable to implement cache memory using DRAM because high capacity cache memories could then be provided at relatively little cost. However, a cache memory implemented using DRAM""s would be inaccessible at certain times during a refresh of the memory cells in the DRAM, As a result of these problems, DRAMs have not generally been considered acceptable for use as cache memory or for other applications requiring immediate access to system memory.
Attempts have been made to use DRAM as cache memory, but these attempts have not been entirely successful in solving the refresh problem. As a result, these prior art devices are not always available for a memory access. These prior art devices have attempted to xe2x80x9chidexe2x80x9d memory refreshes by including a small SRAM to store one or more rows of DRAM data during refresh of a row being addressed. However, in practice, there are still some situations in which these prior art devices may not be accessed, thus suspending the operation of a processor or similar device.
Another approach to allowing DRAM to be used as cache memory is to use a dual-ported DRAM, which includes a second data path and a second set of digit lines. This architecture allows one data path and its associated sense amplifiers to be dedicated to refresh operations. As a result, data can always be read from or written to the DRAM through the other data port. Although dual-ported DRAMs are fairly effective in allowing DRAMs to be used for cache memory, such DRAMs are very large, and hence expensive, because the DRAM array must be nearly twice as large as a conventional DRAM of the same capacity. Thus, the large size and resulting expense of dual-ported DRAMs detracts from the very reason they are proposed for use as a substitute for SRAM caches memories.
There is therefore a need for a DRAM that effectively hides memory refreshes under all memory access situations so that the DRAM may provide relatively inexpensive, high capacity cache memory.
A DRAM being refreshed may be accessed for a read or write without requiring that the access wait for completion of the refresh. The DRAM includes a set of sense amplifiers in addition to the set of sense amplifiers normally provided in a DRAM. In the event a memory access command is received during a refresh, the additional sense amplifiers are isolated and used to store the data that was stored in a row being refreshed. As a result, the refresh can be aborted without loosing data stored in the row. After the refresh is aborted, the DRAM is accessed in a normal manner, and data stored in the additional sense amplifiers are subsequently transferred back to the row that was refreshed.